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2 nanometer chip era is accelerating

2 nanometer chip era is accelerating

March 05 , 2024 0

From this series of latest developments on the 2 nanometer chip process, it can be seen that, driven by the continuous evolution and development of AI technology, the competition of the 2 nanometer advanced chip process is becoming increasingly fierce. In the future, as the problems of yield, cost and ensuring the sustainability of production continue to be solved, the era of 2-nanometer chips is accelerating.

Nanoprocess Background

At present, after the continuous introduction of the 3-nanometer chip process into mass production, 2-nanometer chips are becoming the new competition heights of the major giants.

Recently, as the "most radical" innovative application giant in the field of mobile consumer electronics, Apple was revealed to be designing chips using TSMC's next generation 2nm N2 process. A leaked document about Apple from South Korea shows the following words: "TS5nm, TS3nm, working on TS2nm".

In fact, in addition to TSMC, Samsung, Intel and other chip foundry giants have obtained 2 nanometer chip orders. Overall, compared with the 3-nanometer chip process, 2-nanometer is not only pouring into more chip foundries, but also more upstream and downstream giants of the industrial chain are accelerating the layout of 2-nanometer chip technology.

Giants Have Laid Out 2 Nanometer Chips

In the past few decades, the semiconductor industry "waves", and finally achieved TSMC, Samsung, the two main promoters of advanced chip technology.

Among them, TSMC is the leader in advanced chip technology. In recent years, TSMC has invested most of its funds in the research and development of 2 - and 3-nanometer and more advanced process technologies.

In the 2nm chip production capacity layout, TSMC is currently building two 2nm chip factories, and the Baoshan P1 wafer Fab located in Hsinchu Science Park will be the first to mass-produce 2nm, and the installation of equipment will begin in April 2024 at the earliest. The Kaohsiung plant will follow suit, with production expected to begin in 2025. In addition, TSMC's third 2nm plant, Baoshan P2 plant planning, is expected to be determined this year.

Samsung was the first to begin mass production of 3nm, or SF3, chips, and the first chip giant to shift to a new transistor architecture called Gate-All-Around (GAA). Although Samsung's 3 nm yield is not satisfactory, it is also an active promoter of 2 nm chips. It is reported that Samsung is building a cutting-edge SF2 GAAFET process and intends to surpass its biggest competitor - TSMC.

At the recent Direct Connect event, Intel also announced a "4-year 5-process node promotion plan", including the development node of 2-nanometer chips, and emphasized the development goal of becoming the world's second foundry plant by 2030.
Intel has already disclosed its plans to mass-produce 20A "2-nanometer" chips in 2024. The chip will feature all-new RibbonFET transistors to replace the existing FinFET architecture and bring new interconnect innovations such as PowerVia technology. From the timeline, Intel seems to be the first company to realize the 2-nanometer chip process, but its plan also faces a number of practical challenges.

In addition, Japan's Rapidus also plans to start producing 2-nanometer chips in 2027, joining the competition with chip contract manufacturers such as TSMC and Samsung Electronics. Although the company lacks the deep advanced chip production attritions of TSMC and Samsung, under the promotion of the Japanese government, it has introduced more and more "supporters" from applied process research to advanced chip manufacturing, such as IBM and IMEC, a Belgian research institution.

The Technical Reserve OF Nano-Chip Is Continuously Improved

At present, the technology reserve of the entire industrial chain is also constantly improving, from equipment manufacturers, material suppliers to chip design companies, the entire semiconductor industry is actively responding to this technological change to ensure that it can remain competitive in the era of 2-nanometer chips.

Among them, the lithography machine is an important part. In December 2023, ASML, the world's largest lithography machine manufacturer, revealed that it has begun to deliver the latest generation of "0.55 numerical aperture" EUV lithography tools to Intel Corporation in the United States, which will be used for the production of 2nm process chips.

It is reported that ASML plans to produce 10 2nm EUV lithography machines in 2024, of which six have been ordered by Intel. Although Intel has to "slightly lose" TSMC and Samsung in the advanced chip process, its access to a maximum 2nm EUV lithography machine also brings more uncertainty to the future advanced chip process competition.

At the same time, backside power supply (BSPDN) technology, which is regarded as a key technology for the realization of 2-nanometer chip technology, has recently made progress. Recently, South Korean media reported that it has been confirmed that the backside power supply (BSPDN) technology being developed by Samsung Electronics has achieved a new breakthrough, and will be applied in the 2nm chip process in 2025 in advance.

Intel is also actively developing backside power technology to regain its leadership in process technology. The company plans to use PowerVia in combination with a 20A node (2 nm) RibbonFET (omnidirectional gate) transistor. By using BPD, the device achieved a 6% performance improvement (Fmax), 90% unit utilization, and more than 30% voltage drop reduction.

TSMC also revealed at the previous legal conference that it has developed a backside power rail solution in the N2, which is most suitable for high-performance computing (HPC) related applications. On top of the baseline technology, the back line will increase speed by 10 to 12 percent and logic density by 10 to 15 percent.

In addition, on the transistor architecture, there is a recent supply chain news that TSMC will use GAA (full gate surround) technology to produce 2nm process nodes as scheduled, the Baoshan P1 wafer Fab located in Hsinchu Science Park will start installing equipment as early as April, and the P2 plant and Kaoxiong plant will start producing 2nm process chips using GAA technology in 2025.

2nm Chip Order Snatch War Officially Opened

With the continuous progress of semiconductor technology, the chip process is about to enter a new milestone - 2 nm. Compared to previous processes, 2-nanometer chips can provide higher performance and lower power consumption, bringing better performance and energy efficiency to future electronic devices. However, 2-nanometer chips are very expensive.

Earlier, analysts at International Business Strategies reported that manufacturers transitioning to a 2nm process increased their costs by 50% compared to a 3nm process, resulting in a cost of $30,000 per 2nm wafer. The increased cost of fabs, mainly due to the increase in the number of EUV lithography tools, has significantly increased the cost per wafer and per chip, and these costs are naturally passed on to consumers.

However, relative to the lack of orders in the mass production of 3-nanometer chips, the downstream application needs of 2-nanometer chips seem to be much clearer. It is reported that TSMC has shown the process test results of the N2 prototype to major customers such as Apple and Nvidia. And Samsung is not to be outdone, by launching 2nm prototypes and offering discounted prices to attract customers such as Nvidia. Qualcomm has planned to use Samsung's SF2 (2nm) process for the next generation of high-end mobile phone chips.

There is no doubt that Apple is an absolute "fan" of the 2-nanometer chip process. The industry even expects that Apple will monopolize TSMC's 2nm production capacity, which is expected to be put into production in the second half of 2025. Compared with the 3nm process, 2nm is expected to achieve a 10% to 15% improvement in performance at the same power consumption, or a 25% to 30% reduction in power consumption at the same computing speed.

Recently, Samsung's 2 nanometer chip also welcomed good news, winning the first 2nm process AI accelerator chip production order from Japanese AI giant Preferred Networks Inc. (PFN). The order also includes complementary HBM memory and advanced packaging services.

Intel, which is determined to enter the field of chip foundry, recently announced a 4-year 5-node process promotion plan, not only Arm for its advanced chip process platform, but also Microsoft to send Intel 18A process orders.

It is worth mentioning that even the Japanese company Rapidus has also obtained a 2 nanometer chip order. A Japanese government-backed semiconductor research group will partner with U.S. startup Tenstorrent Inc. Collaborating to design its first advanced artificial intelligence chip with the help of semiconductor industry legend and "chip god" Jim Keller. The AI chips will be produced by Rapidus, a Japanese company.