What is memory, about memory introduction-joinwin science popularity

A memory chip is a semiconductor chip used in a computer system to store temporary information as well as data needed for programme execution. It stores data in cells with addresses through integrated circuits, is very fast to read and write, and usually has a large capacity. During computer operation, the CPU needs to read and write to the memory frequently, so the speed and performance of the memory chip are crucial to the stability and efficiency of the entire computer system.

The storage principle of memory chips is to store and read data through the change of binary signals. Memory chips use the bit (bit) as the smallest unit and combine a sequence of bits to form a binary code, which in turn enables the storage and reading of data. In a memory chip, data is organised in an address space where each data cell has a unique address. Through the addressing unit, the CPU can access any data cell in memory.

A memory chip usually consists of a memory cell, an address line and a control line. The memory cell is the most basic unit in memory, used to store binary data bits; the address lines are used to transmit the memory address information sent by the CPU; and the control lines are used to achieve the control and synchronisation of read and write operations. In general, memory chips are composed of multiple memory cells, each of which includes a certain number of binary data bits, as well as an address pin and one or more control pins.

Memory chip is one of the important parts of electronic devices, which has a wide range of applications in many fields. In computer systems, memory chips are used to temporarily store information such as programmes, data and operating systems, and are the basis for the normal operation of computers. In mobile devices such as mobile phones, memory chips play a similar role, used to store temporary data and related resources needed to run the application.

Memory sticks cannot work alone in an entire computer system and require a corresponding Memory Controller and a corresponding power supply module for the memory stick. The earliest memory controllers were in North Bridge chips, but as North Bridge chips have been phased out of the market, the memory controllers have been moved inside the processor.
It should be noted that not all computer systems use memory sticks, such as Ultrabooks, where the memory particles are mounted directly on the motherboard, so that the motherboard is designed to accommodate some of the design of the memory stick itself, and to provide a similar SPD chip, or to embed its contents in the BIOS. Some computer systems use processors that have high-speed memory chips built into the processor itself, and the design of the external memory slots can be omitted if the built-in memory capacity meets the requirements.

Are two single Rank memory sticks the same as one double Rank memory stick?
Do memory sticks with x16 memory particles have ECC?
What are the main types of signals included in the RCD parity check of RDIMMs?

SDRAM stands for Synchronous Dynamic Random Access Memory.
Synchronous: It means that read and write access to memory particles is based on some synchronous clock.
Dynamic: Dynamic means two things, firstly, the content of the memory cell storage needs to be refreshed periodically, and secondly, the content of the memory cell will be lost in the state of power down and not refreshed.
Random Access (Random Access): read and write operation delay does not vary with the physical location of the storage media access.
Note that DRAM is often preferred to SDRAM because there is very little Asynchronous DRAM available.

DDR stands for Double Data Rate, the full name should be DDR SDRAM, DDR memory is a type of SDRAM, before DDR we had Single Data Rate SDRAM, Double Data Rate means that data can be transferred on both the upper and lower edges of the clock signal, Single Data Rate means that data can only be transferred on the upper and lower edges of the clock signal. Double Data Rate means that data can be transferred on both the upper and lower edges of the clock signal, while Single Data Rate means that data can be transferred only on the rising edge of the clock signal.

DIMM stands for Dual In-Line Memory Module. DIMM is an abbreviation for Dual In-Line Memory Module, which means that there are gold fingers on the front and back of the printed circuit board of the memory stick in contact with the memory stick slot on the motherboard, and this kind of structure is known as DIMM, so the memory stick is also called DIMM stick, and the memory slot on the motherboard is also known as DIMM slot.
Since there are DIMMs, it is assumed that there are SIMMs (Single In-Line Memory Module), and interested readers can search for them on the Internet.

The use of ordinary memory sticks in the laptop will make the laptop size is too large, while the direct use of memory particles is not easy to expand and maintenance, the gap between the two is filled by SODIMM, SODIMM is the abbreviation of Small Outline DIMM, meaning small size DIMM, generally used in notebooks or all-in-one PCs!

DDR is actually the first generation of DDR, which can also be referred to as DDR1.
DDR2, DDR3 and DDR4 refer to the second, third and fourth generations of DDR. They differ in voltage, rate, clock topology, control and address line topology, and supported commands, which will not be covered here unless the reader requests it. You can also refer to the official JEDEC specifications for each generation.

Several DIMMs can be connected to a set of buses called a Memory Channel.
The data and checksum ECC are bidirectional signals and connect all DIMMs in the Memory Channel. e.g., the data signal, DQ0, will connect DQ0 of DIMM0, DQ0 of DIMM1...
clock, the control and address signals are unidirectional, sent by the memory controller and received by the memory particles. The address signals will connect all DIMMs.
The clock and control signals will not be connected to all DIMMs, but may only be connected to a certain DIMM or several DIMMs. e.g. Clock signals, CKE signals, ODT signals, CS_N chip-select signals etc. Please refer to the reference lines of the system design for specific connections.

Memory particles (DRAM Device) are often confused with RAM, which is often confused with memory sticks. Strictly speaking, memory particles are DRAM Devices, DRAM Chips, a type of chip that conforms to JEDEC standards. Broadly speaking, packaged memory chips can also be referred to as memory particles. Due to the advent of 3DS, it is possible to have more than one DRAM chip (die) in a package. Usually, however, there is only one Die in a package.
It is important to note that the main JEDEC DDR4 specification is for DRAM Devices, not memory sticks. The signal timing diagrams presented therein also do not refer to the timing on the memory slots, but to the timing of the input and output ports of the memory chips.

As introduced earlier a memory channel can have more than one DIMM, if for some reason we can only allow a maximum of three DIMMs to exist on the motherboard, for example, from the fourth DIMM, we do not have enough space, or the quality of the signals is degraded due to the length of the excessively long, and so on. But what about performance reasons, when we need six DIMMs in one memory channel? This is where the concept of Rank is introduced, which is like a logical DIMM, where we can take the memory particles of two physical DIMMs and put them all on a single memory board, giving us twice the memory capacity in a single memory stick. We call this logical DIMM a Rank, and in order to support multi-RANK memory sticks, we need to define multiple CS_N chip select signals on the physical DIMM interface so that the corresponding Rank can be selected.
To summarise, a Rank is a group of memory particles whose CS signals are linked together and controlled by a single CS_N signal from the memory controller, together forming a 64bit (without ECC) or 72bit (with ECC) bit-width memory array, which together carry out the instructions issued by a memory channel.

The data bit width of the memory stick in x86 architecture is 64bit, which means that one clock cycle can transfer 64bit of data if only the rising edge is considered. If Double Data Rate is used, two 64-bit data transfers can be made in one clock cycle.
If the memory stick supports ECC checksum function, it needs an additional 8bit width. So, memory sticks that support ECC function have 8bit of checksum data in addition to 64bit of data.
Currently, the mainstream DRAM Devices have 4bit, 8bit and 16bit data widths, corresponding to x4, x8 and x16 types of memory particles respectively. If we use x4 memory particles to construct a memory stick with ECC function, we need (64+8)/4 = 18 x4 memory particles. Whereas if we use x8 memory particles, we need only 9 of them.
This design is only a single Rank design, if it is a multi-Rank design, more memory particles will be needed. For example, for a 2 Rank memory stick with ECC, if we use x4 memory particles, then we need a total of 36 x4 DRAM Devices.
It is important to note that if x16 DRAM particles are used, the ECC function cannot be implemented, because 4 x16 DRAM particles form exactly one Rank without ECC, and adding one more will result in an extra 8 bits of bit width that cannot be matched. Therefore, most of the x16 memory is used in SODIMMs for notebooks. Of course, if you must add ECC function, you can consider adding an x8 chip.

The first letter R in RDIMM is actually the extra chip mentioned earlier, called a Registering Clock Driver. Memory sticks without this chip are generally referred to as UDIMM (Unbuffered-DIMM). This registering chip is mainly used to buffer the clock/control/command/address signals. The main purpose of caching is to solve the problem of signal quality as well as overloading.
RCD (Clock Cache Register Chip):
In addition to this, a typical RDIMM will support ECC function and command/address parity (CA Parity).

In order to support more Ranks on a single physical DIMM, we improve the quality of the data signal by passing it through the Data Buffer chip instead of connecting it directly to the DRAM Devices.

The following picture shows the memory chip display：