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What Is General Purpose Pcb?PCB Design Sharing

What Is General Purpose Pcb?PCB Design Sharing

September 20 , 2023 0

With the development of electronic technology and printed circuit board manufacturing technology, circuit boards have become an important part of electronic products, electronic products manufactured with printed circuit boards have high reliability, good consistency, high mechanical strength, light weight, small size, easy to standardize and other advantages. However, as electronic product design is more and more complex, the density of printed circuit boards is also increasing, so the test and repair of printed circuit boards is also more and more difficult. In order to improve the degree of automation of the testing and repair of printed circuit boards, this paper designs a general-purpose circuit board automatic test system, the system from the needle bed to the various aspects of the test software are used in the open design, the versatility is very strong.

General Structure Of The System

The main purpose of this system is to test whether the circuit board is working properly, which is achieved by testing the key signals on the board. Therefore, the task of this system is to collect the key signals on the circuit board and analyze the test results through the software on the PC. The system is divided into 3 parts: pin bed, signal acquisition and transmission module, and test software. As a general test system, strong generality is considered in all 3 parts.
The block diagram of this automatic test system is shown in Fig. 1. The working principle of the system is as follows: the signals to be tested are exported through the needle bed, the FPGA collects the signals to be tested by controlling the multi-channel analog switches, and transmits the data to the PC through the corresponding protocols, and then the automatic test software is used to test whether the signals are normal or not.
Due to the large difference in the frequency of the signal to be tested, there are DC signals, there are pulse signals with frequencies higher than 103MHz, as well as a variety of frequency signals in between, so the system adopts low-frequency and high-frequency 2 groups of signal sampling circuits to adapt to the needs of different signal acquisition.

Main Chip Introduction

The main chips used in this system are: the main chip EP2S63, AD sampling chip AD7864 and AT84AD331. the following is a brief introduction to these three chips:

　　EP2S63 is altera's Strati series of FPGAs, the series of FPGAs using advanced 93nm production process; the FPGA performance to a new height, the series is the industry's fastest, highest density FPGAs. EP2S63 has as many as 84 dedicated LVDS differential logic receiver channels, each LVDS channel data transfer rate up to 1Gb/s. Its internal memory is up to 1Gb/s, and it can be used as the main chip. The EP2S63 has up to 84 dedicated LVDS differential logic receiver channels, each with a data rate of up to 1Gb/s. It has a dedicated high-speed digital phase-locked loop circuitry that generates clock signals that can be used by the ADC circuits.

　　The AD7864 is a low-speed, low-power, 12bA/D converter with four channels of simultaneous sampling. It has a 12-bit A/D converter, can simultaneously sample 4 input channels, and has 4 sample, hold amplifier; single power supply (+5V), a number of conversion voltage range, for each analog input channel have over-voltage protection circuitry; 4-channel simultaneous operation, the maximum sampling rate of 133kHz.

　　AT84AD331 is a high-speed acquisition chip produced by Atmel. The device integrates two (I and Q) independent ADC, with 8b conversion accuracy, each channel has a lGs / s sampling rate, in interleaved mode sampling rate up to 2Gs / s. The chip based on high-speed applications, analog inputs, digital clock inputs, digital clock outputs, data outputs, synchronous clock outputs are used in differential mode. The data output adopts the LVDS standard, and its transmission rate is up to 1Gb/s. Using its internal multiplexer, the output data rate can be reduced, and it can also be conveniently connected directly with many types of high-speed FPGAs. When 1:2 mode is used, the output data rate is reduced to 533Mb/s, which can meet the requirements of most FPGAs to receive data.

System Design

Needle Bed Design

The needle bed is an important part of the circuit board test system, and is the platform for circuit board signal export. The versatility of the needle bed is poor, generally each circuit board corresponds to a specific needle bed, which makes the versatility of the system is greatly limited. In order to make the needle bed have a certain degree of universality, some improvements have been made to the relevant components of the needle bed in this system:
(1) Probe design. The probe is a spring-loaded probe designed on the basis of the probes currently available on the market, which is easy to fix and convenient for signal export:

　　One end of the probe is the probe, is in contact with the circuit board, and export the signal part; the other end is the fixed seat, is an insulator, hollow, containing a spring, so that the probe can be retracted; the middle of the signal export terminal. In order to reduce the interference between the various signals, the wires are shielded. In order to adapt to different signal requirements, according to the thickness and allowable signal bandwidth requirements of the probe is divided into a variety of models, the use of the probe according to the need to choose the model.

　　(2) Probe fixation: in this system of the needle bed, the probe is fixed using two identical probe fixed plate and 4 baffle plate composition, fixed plate and probe fixed schematic diagram in Figure 2b and Figure 2c: fixed plate size and to be measured on the same board, the board fixed hole location should be determined according to the technical documents to determine the board, the size of the holes need to be based on the selection of the type of probe to decide. The baffle plate can be moved and adjusted on the whole base of the needle bed to adapt to the fixing requirements of different sizes of circuit boards; the width of the baffle plate is 233mm for the front and rear two, and 73mm for the left and right two.

Signal Acquisition

There are three main types of signals output from the circuit board to be tested: power supply signals, pulsed digital signals, and level shifted signals. In addition, there are some higher-frequency analog signals, such as audio and video signals, such signals are generally not used as key test signals, if you need to test the acquisition of high-frequency signals. Among them, the power supply signal and level change signal can be regarded as DC signals to collect, with AD7864 to complete the acquisition. Pulse digital signals of high frequency, often dozens of megahertz or even hundreds of megahertz, the need for high-speed AD (this system is used in the AT84AD331) to capture, and the need to measure the frequency. Therefore, this system signal acquisition is divided into two parts: low-frequency and high-frequency, which are described below:

(1) low-frequency part. This part of the main acquisition of power signals and level conversion signals, using AD7864 as the acquisition chip. AD7864 has an on-chip clock, read-write allow logic, a variety of channel selection and internal precision 2.5V reference voltage, which makes its interface with high-speed processors has become very simple. AD7864 converted data reading using the conversion of the data read after reading the data, its reading The timing is shown in Figure 3.
(2) High-frequency part. It is mainly the acquisition of pulse digital signals, including frequency measurement and signal acquisition in two parts. The frequency of the pulse digital signal is an important parameter to determine whether the circuit board is working properly, so to determine whether the frequency of the pulse signal is normal or not is the necessary work of this test system. This system is the signal to be tested into the FPGA and 53MHz high-precision clock at the same time to start counting, after a period of time, through the count value of the two signals to calculate the pulse signal frequency. Signal acquisition is to AT84AD331 as the acquisition chip. the connection between AT84AD331 and EP2S63 is shown in Figure 4.
As the AT84AD331 input signal is differential signal, and the peak-to-peak value of the signal does not exceed 533 mV. the signals to be measured on the board are single-ended and the peak-to-peak value of the signal is generally between 4V and 5V. The system uses a 13:1 transformer coupling input method, which can complete the conversion of single-ended signals to differential signals, and make the signal voltage to meet the requirements.

　　The operations of reading, combining, sorting and storing LVDS signals are completed inside the FPGA. In general, the value of the stored sampling points is within 1333, and then the value of these sampling points is calculated to obtain the actual voltage value.

Data transmission and control protocol

　　There are more signals to be measured in the system, the low-frequency and high-frequency parts are 32 respectively, while there is only one data acquisition chip for each of them, and each of the signals is time-shared by the FPGA-controlled analog switch. In order to make the data storage, transmission and control of each channel in an orderly manner, an operating state control module and a data storage module (hereinafter referred to as registers and data memory) are set up in the FPGA for each signal. All the commands for the control process in this system are issued from the PC, and the FPGA receives the control commands and performs the corresponding operations according to the commands.

　　(1) Introduction of registers and data memory. FPGA has a 5bit control register, 12bit final result register and 16bit raw data memory for each signal. In addition in the high-frequency part also has a public high-speed sampling data memory, the size of 1kB, and its corresponding an 8bit control register. 5bit control register for each channel has only one, the register D3 bit for the data ready flag (1 valid), the remaining four bits for the control bit, the function of each bit see Table 1, each bit is 1 for sure, each bit can be changed through the control instructions sent from the PC. Each bit is 1 for sure, and each bit can be changed by the control instruction sent from the PC. The FPGA can only write 1 to the D3 bit to indicate that the data is ready. The value of this register is 33333B after power-up or reset.
There is also only one 12-bit final result register for each channel, and the value of this register is the final result sent to the PC. The data in this register is stored differently in the low frequency and high frequency sections: the low frequency section stores the average of the 13 sampling results, and the high frequency section stores the calculated frequency value.

　　16bit raw data memory, the number of its low-frequency and high-frequency part is not the same: high-frequency part is generally 2, respectively, used to store the standard and to be measured clock count value; low-frequency part of the 13, used to store the value of the 13 sampling points, the value of the 12bit final result register is based on the average of these 13 data.

　　High-speed sampling data memory is common to the high-frequency part of the 32-channel, due to the relatively large amount of data sampled by the waveform, the system is designed to allow only 1 channel signal sampling at the same moment, the number of sampling points can be set (up to 1K), until all of these data are sent out before the next acquisition can begin.
Among them, D7～D4 is the number of points set for data acquisition, 3333B means 64, 1111 means 1324, and the step is 64. D3～D1 is the interval set for data extraction, 333 means the extraction interval is 3, and all the data are valid; 111 means the extraction interval is 28, i.e., one point is extracted for every 28 points, and the step is 4. The purpose of setting these bits is to adapt to the requirements of signal frequency, and prevent the data collected is not enough for one channel, so that the data collected is not enough for one channel. The D3 bit is a flag bit, and its function and operation are exactly the same as the corresponding bit of the 5-bit register. D3 bit is a flag bit with the same function and operation as the corresponding bit of the 5-bit register, and the register is divided into two settings, the high 4 bits and the low 4 bits.

　　(2) Introduction of control commands. The control commands in this system are all issued by the PC, with a total of 8 commands: select control register 1 (low-frequency portion); select control register 2 (high-frequency portion); select control register 3 (high-speed sampling portion); write control register data; read data 1 (low-frequency portion); read data 2 (high-frequency portion of the frequency value); read the waveform sampling data; and start/stop the test.

　　The control words sent by the PC are all 8-bit, of which the high 3 bits are the control command words to distinguish the 8 commands, and the low 5 bits are the auxiliary functions, as shown in Table 3.The FPGA receives the command signals from the host, and then performs the corresponding operations according to the commands.
(3) Brief description of the data transmission process. The communication with the PC in the system adopts the RS232 interface, and the data transmission is in full compliance with the RS232 standard. The data transmission process is briefly described as follows: after the system starts, the first self-test to determine whether the system is working properly; after the system is working properly, the PC through the test software to configure the various registers within the FPGA; and then send the start command to start the effective collection of the various signals; the collection of the completion of the return information to the PC, the PC according to the need to test the software from the FPGA to read the data of the corresponding channel, the data will be transferred from the FPGA to the PC, and the data will be transferred from the FPGA to the PC. Read the corresponding channel data through the test software from the FPGA as needed, the data will be calculated and compared with the standard value and arrive at the test results. It is also possible to read the original data of a certain channel and collect the waveform of a certain channel signal according to the need. Inside the FPGA also has a key signal (power) monitoring: any power signal is not normal, then re-acquisition, if three times the acquisition results are not normal, then directly shut down the board's power supply to avoid damage to the circuit board, and send a message to the PC power supply is not normal, and give the channel number of the abnormality.

Frequently asked questions about automated test systems for circuit boards

Which model is used for circuit board testing?

The most commonly used inspection systems are Automated Optical Inspection (AOI) and Automated X-Ray Inspection (AXI).AOI is a visual inspection method used for PCBs. In an AOI system, one or more static or video cameras scan the board.

How do I test a PCB circuit?

To test a circuit board for shorts, you need to check the resistance between different points in the circuit. If the visual inspection doesn't reveal any clues about the location or cause of the short, grab a multimeter and try to trace the physical location on the printed circuit board.

How do PCB test points work?

Using a PCB design tool to assign test points to a board allows the designer to add test points automatically or manually during the iteration process once the parameters have been set. Test points are typically assigned first to any available through-hole pins and then to vias.

What is an Automated Test Equipment System

Automated test equipment (ATE) or automated test equipment is a computerized machine that uses test instrumentation to perform and evaluate the results of functional, performance, quality and stress tests performed on electronic devices and systems.

What is an ATE board?

ATE Load Board/DUT Board/Interface Board. Test Equipment Load Board/Interface Board. A load board, interface board, or DUT board is a circuit board designed to be used as an "interface" circuit between an automatic test equipment (ATE) and a device under test (DUT).

Why use an ATE?

ATE systems are designed to reduce the amount of test time required to verify that a particular piece of equipment is working properly or to quickly find faults in a component before it has a chance to be used in a final consumer product.