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What's A Latch, A Flip-Flop? Difference Between Latch And Flip Flop

What's A Latch, A Flip-Flop? Difference Between Latch And Flip Flop

October 05 , 2023 0

latch (electronic)

Latch (latch) is a level-triggered storage unit, the action of data storage depends on the level value of the input clock (or enable) signal, only when the latch is in the enable state, the output will change with the data input.

Simply put, the latch has two inputs, an active signal EN, an input data signal DATA_IN, and an output Q. Its function is to pass the value of DATA_IN to Q when EN is active, which is the process of latch.

Flip-Flop

A Flip-Flop (abbreviated as FF), also known as a bistable gate, also known as a bistable flip-flop, is a digital logic circuit that can operate in two states. Flip-flops maintain their state until they receive an input pulse, also known as a trigger. When an input pulse is received, the flip-flop output changes state according to a rule and then remains in that state until the next trigger is received. Flip-flops are sensitive to pulse edges and their state changes only at the instant of the rising or falling edge of the clock pulse.

Difference Between Latch And Flip-Flop

Latch and flip-flop are binary memory devices with memory function, which is one of the basic devices to form various timing logic circuits. The difference is that latch is related to all its input signals, when the input signal changes latch changes, there is no clock terminal; flip-flop is controlled by the clock, only when the clock is triggered to sample the current input and produce an output. Of course, since both latch and flip-flop are timing logic, the outputs are not only related to the current inputs but also to the outputs of the previous time.

(1) Latch is triggered by level and controlled asynchronously. When the enable signal is valid, latch is equivalent to the path, and when the enable signal is invalid, latch maintains the output state; DFF is triggered by the clock edge and controlled synchronously.

(2) latch is sensitive to the input level, affected by the wiring delay, it is difficult to ensure that the output does not generate burrs, while DFF is not easy to generate burrs.

(3) If gate circuits are used to build latch and DFF, latch consumes less gate resources than DFF, which is the superiority of latch over DFF. Therefore, the integration of using latch in ASIC is higher than DFF, but it is the opposite in FPGA, because there is no standard latch cell in FPGA, but there is DFF cell, and one LATCH needs more than one LE to be realised. latch is level-triggered, which is equivalent to having an enable terminal, and it varies with the inputs after activation (when the enable level is active). In the non-enable state latch maintains the original signal, which can be seen and flip-flop difference, in fact, many times latch is not a substitute for FF.

(4) latch makes static timing analysis extremely complex.

The general design rule is to avoid latch in most of the designs. latch will make the timing of the design chaotic, and it is very hidden and hard to check. latch's biggest harm is that it can't filter the burrs, which is extremely dangerous for the next level of the circuit. So, wherever you can use a D flip-flop, don't use latch.

There are some places where there is no clock, so you can only use latch. For example, if you now connect a clk to the enable side of the latch (assuming it is enabled high), the setup time needed for this is the time it takes for the data to be before the falling edge of the clock, but if it's a DFF then the setup time is the time it takes for the clock to be on the rising edge. This means that if the data is later than the control signal, only latch can be used, in which case the aforementioned latch timing borrow. is basically equivalent to borrowing a high level time. In other words, the latch timing borrow is also limited.