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TSMC China Technology Forum: Advanced Process/Packaging Demand Is Strong, Cost Pressure Behind Expansion

TSMC China Technology Forum: Advanced Process/Packaging Demand Is Strong, Cost Pressure Behind Expansion

May 30 , 2024 0

Thanks to the surging demand for advanced process chips under the global artificial intelligence (AI) boom, TSMC ended three consecutive quarters of decline in the first quarter of 2024 and achieved its fastest sales growth since 2022. At the just-concluded TSMC China Technology Forum, TSMC shared its latest technological progress and roadmap in the fields of process, packaging, silicon photonics, etc., and the "Electronic Engineering Album" was also sorted out, hoping to help readers see the future development trend of the semiconductor industry.

Deep Cultivation OF Advanced Process Technology

Looking forward to achieving more than 200 billion transistors on a single chip in the next few years, and reaching more than 1 trillion transistors through 3D packaging, is TSMC's ambitious technology breakthrough plan.

As the first 5-nanometer fab to begin mass production in 2020, TSMC continues to strengthen its 5-nanometer process family by introducing technologies such as N4, N4P, N4X and N5A, while the latest N4C technology is suitable for a wider range of applications. The N4C, which continues N4P technology, reduces bare crystal costs by up to 8.5% with low barriers to use, and is scheduled for mass production in 2025. N4C provides a more area efficient base IP and design rules that are fully compatible with the widely adopted N4P, so customers can easily move to N4C. The process also improves yield by reducing bare crystal size, providing a highly cost-effective option for value-emphasizing products to migrate to TSMC's next generation of advanced technologies.

Driven by mobile and HPC applications, its 3 nm process, as the first process technology in the semiconductor industry to achieve high volume production and high yield, will also quickly and smoothly achieve ramping. In 2024 and 2025, TSMC will continue to introduce N3P and N3X to enhance the process technology value, providing additional performance and area advantages while maintaining design rule compatibility with N3E to maximize IP reuse. The latest news shows that N3P has completed certification, and the yield performance is close to N3E.

The 2nm node using Nano Sheet technology is expected to achieve technical mass production in 2025, and the second generation N2P and A16(1.6nm) are expected to be mass-produced in 2026. Compared to the first-generation N2 process, N2P can reduce power consumption by 5%-10% at the same frequency and number of transistors, and improve performance by 5%-10% at the same power consumption and number of transistors. It shows that transistor architecture has evolved from planar FET to fin FET(FinFET), and will usher in another change to the development of nanosheets.

In addition to nanosheets, there are vertically stacked nFET and pFET, that is, CFET-shaped transistors, which may be a development direction for transistor upgrades. TSMC has been actively studying the use of CFET architecture for the next technology upgrade, which the industry generally believes will be "the next generation of new transistor architecture innovation after the Nano Sheet architecture." According to the prediction, considering the complexity of the wiring and process, the density gain of CFET is likely to be between 1.5-2 times.

In addition to CFET, TSMC has also achieved breakthroughs in the field of low-dimensional channeling materials, such as inorganic nanotubes or carbon nanotubes such as WS2 or WoS2, helping to further drive size reduction and energy consumption reduction. This also means that TSMC will introduce CFET into more advanced Emie-level processes in the future, and will continue to promote more advanced transistor architecture innovation to achieve the goal of accommodating more than 200 billion transistors in a single logic chip.

Introducing new interconnect technologies to improve interconnect performance is also part of TSMC's ambitious plans, including: introducing a new through-hole solution in the copper-based interconnect sector to reduce through-hole resistance by an additional 25%; The new through-hole etched stop layer reduces the coupling capacitance by about 6%; The new copper barrier can reduce copper wire resistance by about 15%. In addition to copper interconnects, TSMC is also working on a new metal material containing an air gap that can reduce coupling capacitance by about 25%, and a new intercalated graphene material that can significantly shorten interconnect delay.

Advanced Packaging Technology Accelerates Progress

In order to further develop the minization technology to achieve smaller and better transistors in the System on a Chip (monolithic SoCs), TSMC has developed 3DFabric technology, hoping to increase the number of transistors in the system by five times or more by leveraging the advantages of heterogeneous integration.

Currently, the TSMC 3DFabric technology portfolio consists of three platforms: TSMC-SOIC ®, CoWoS® and InFO. Among them, the SoIC platform is used for 3D chip stacking, and provides two stacking schemes, SOIC-P and SOIC-X. From a technical point of view, SoIC chips can be integrated into CoWoS or InFO according to product integration needs.

For example, SoIC-P is a Bumped based stacking scheme, which is suitable for cost-sensitive applications such as mobile applications. SoIC-X is a Bumpless stacking scheme, either with the 9 micron bond spacing of the existing "front to back" stacking scheme for wafers or the 3 micron bond spacing of the "front to front" stacking scheme for wafers that will be available in 2027. The bare to bare (die-to-die) interconnection density is more than 10 times higher than the micro-convex F2F stacking scheme with 40 microns to 18 microns. SoIC-X is particularly suitable for HPC applications with high performance requirements, and TSMC expects to have 30 customer streaming chips by the end of 2026.

CoWoS platform includes the most mature silicon intermediate-layer based COWOS-S, as well as organic intermediate-layer based COWOS-L and COWOS-R three solutions, through the integration of advanced SoC or SoIC chips with HBM, It can help bring high-specification AI chips to market - in the Blackwell AI accelerator launched by TSMC and NVIDIA, the world's first mass-produced CoWoS-L product integrates 2 N5 SoCs and 8 HBM stacks into one module; The AMD MI300A/MI300 X is the first to use CoWoS and SoIC-X technology.

TSMC has already delivered SOics through the COWOS-S production line and plans to develop an 8x mask-size CoWoS containing A16 SoIC chips and 12 HBM stacks, supporting a larger 120mm x 120mm substrate with 40x more computing power, which is expected to be mass-produced in 2027. By the end of this year, TSMC will have achieved more than 150 CoWoS product streams for more than 25 customers.

InFO PoP and Info-3D are for high-end mobile applications, while InFO 2.5D is for HPC core integration. In addition, following the introduction of the N3AE process in 2023 to support early adoption by automotive customers, TSMC continues to meet automotive customers' demands for higher computing power by integrating advanced chips and packages to meet driving safety and quality requirements. TSMC is developing InFO-oS and CoWoS-R solutions to support applications such as Advanced Driver assistance systems (ADAS), vehicle control and central control computers, and is expected to complete AEC-Q100 Level 2 validation in the fourth quarter of 2025.

In terms of System-on-Wafer (SoW) technology, TSMC plans to expand the computing power required for a new generation of data centers with the help of mature InFO and CoWoS technologies, and plans to launch the CowOS-based SoW in 2027, which will integrate advanced SoC or SoIC, HBM and other components.

Special Process Technology

In terms of special processes, as far as the information has been disclosed, this year's technology forum did not introduce many fields such as automobiles, advanced radio frequency, ultra-low power consumption, MCU/ embedded non-volatile memory, CMOS image sensing as 2023, but only focused on the latest progress in the field of silicon photonics.

Silicon photonics are the best choice for co-packaged optics because they are semiconductor compatible and can be highly integrated with EIC/PIC/ switches at the package level, so it is not surprising that they are TSMC's focus. The innovative COUPE(Compact Universal Photon Engine) solution integrates PIC and EIC through the shortest path homogeneous copper-copper interface and enables ultra-high speed radio frequency (RF) signals (200G/λ), with the core benefit of minimal footprint and the presence of grating couplers (GC) and edge couplers (EC) to meet the different needs of customers.

According to the plan, TSMC plans to complete the COUPE verification of the small plug-in connector in 2025, and then integrate it into the CoWoS package substrate of co-packaged optics in 2026, reducing power consumption by 2 times and delay by 10 times. At the same time, TSMC is also exploring a more advanced co-packaged optical solution that integrates COUPE into the CoWoS intermediate layer to reduce power consumption by another five times and delay by another two times.

Capacity Continues To Be Expanded Worldwide

In order to meet the growing demand of customers, TSMC's pace of accelerating the expansion of fabs has shown no signs of slowing down. From 2017 to 2019, the company averaged approximately 2 phases of fab construction per year; From 2020 to 2023, TSMC's average fab construction progress has increased significantly to about 5 phases per year; By 2024, the number of plants under construction has reached seven, including three fabs, two packaging plants, and two overseas fabs.

In terms of layout, Fab 20 in Hsinchu, Taiwan, and Fab 22 in Kaohsiung, both 2nm fabs, have started installation and are expected to be mass-produced in 2025. Construction of three phases of wafer fab in Arizona, the first phase has begun to move into the equipment, is expected to mass produce 4nm wafers next year; The second phase under construction is expected to produce 3nm wafers in 2028; The planned third phase is expected to enter mass production by 2030. The first fab to be built in Kumamoto, Japan, is expected to offer 16/28nm technology in the fourth quarter of this year; The second fab is expected to produce a 6/7nm process in 2027. In addition, TSMC also plans to start construction of a 16nm wafer fab in Germany in the fourth quarter of this year, and is expected to achieve mass production in 2027.

In terms of advanced packaging capacity, according to the plan, by 2026, the compound annual growth rate of TSMC CoWoS production line will exceed 60%, and the capacity at the end of the year will be 4 times that of 2023; SoIC capacity will increase eight times from 2023, with a compound annual growth rate of up to 100%.