With the vigorous development of artificial intelligence and the growth of demand for high computing power and high storage, HBM is showing broad prospects for development, but it also faces challenges such as technical difficulties and insufficient production capacity. In a recent interview with the Financial Times, Kwon Jae-soon, SK Hynix's vice-president in charge of yield, said: "We have succeeded in reducing the time required for mass production of HBM3E chips by 50 per cent. The yield of these chips has almost reached the target of 80 percent."
This is the first time SK Hynix has publicly disclosed HBM3E production information. Previously, the industry expected SK Hynix's HBM3E yield to be between 60% and 70%.
At present, the global HBM market is occupied by three major original manufacturers, of which SK Hynix technology is leading, occupying a dominant position in the market. SK Hynix is Nvidia's sole supplier of HBM3 memory and began mass production of the latest generation HBM3E in March.
Currently, competing suppliers such as Micron Technology and Samsung are developing their own HBM products to compete for the HBM market dominated by SK Hynix. But Micron is the underdog in the HBM market, with only a 10% market share. Samsung Electronics also faces challenges in the HBM space, with its HBM3 yield below 20% and a recent failure to obtain product certification from Nvidia.
Kwon Jae-soon also stressed: "Our goal this year is to focus on producing 8-layer HBM3E. In the age of AI, increasing production becomes even more important to stay ahead of the curve."
However, because HBM manufacturing requires vertical stacking of multiple DRAM, the process complexity is higher than standard DRAM, especially the key component of HBM3E's through-silicon hole (TSV) yield has been low, only 40% to 60%. Specifically, the reasons why HBM3E technology is difficult include the following:
The first is the high-rise stack design: the HBM3E uses a 12-layer vertical stack design, which requires extremely high precision and complex process technology in the manufacturing process. Each additional layer puts higher demands on the manufacturing process, especially in terms of maintaining yield.
The second is through-silicon (TSV) technology: HBM3E uses through-silicon technology to connect DRAM between different layers, which requires very precise equipment and technical support to ensure the stability and speed of signal transmission. The difficulty of TSV process is greater, and the requirements for production equipment and technical personnel are also high.
The third is the application of hybrid bonding technology: While for future HBM4 memory, SK Hynix says that the application of hybrid bonding technology will be delayed, this shows that even the current HBM3E faces the problem of how to effectively combine different materials and components during development. This not only involves material science challenges, but can also affect production capacity and product quality.
SK Hynix plans to supply 12-layer HBM3E products in the third quarter of this year. The 12-storey HBM4 (sixth generation) is scheduled to launch in the second half of 2025, with a 16-storey version expected to enter production in 2026. SK Hynix forecasts that HBM and high-capacity DRAM module products, mainly for AI applications, will account for 61% of the total memory market by 2028.